// Copyright (C) 1953-2022 NUDT
// Verilog module name - descriptor_generate
// Version: V4.0.0.20220525
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         judge outport of standard ethernet packet
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module descriptor_generate
(
        i_clk             ,  
        i_rst_n           ,
                        
        iv_md             ,
		i_md_wr           ,
                        
        ov_pkt_bufid      ,
        o_pkt_bufid_wr    ,
        ov_pkt_bufid_cnt  ,
        
        ov_descriptor     ,
        o_descriptor_wr   
        
);

// I/O
// clk & rst
input                  i_clk;                   //125Mhz
input                  i_rst_n;
// pkt_bufid and pkt_type and outport from lookup_table
input      [199:0]     iv_md;
input                  i_md_wr;
// pkt_bufid and pkt_type to p0
output reg [87:0]      ov_descriptor;
output reg             o_descriptor_wr;
//forward cnt to pkt_centralize_bufm_memory
output reg [8:0]       ov_pkt_bufid;
output reg             o_pkt_bufid_wr;
output reg [5:0]       ov_pkt_bufid_cnt;
//***************************************************
//                    forward
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
	    ov_descriptor    <= 88'b0;
        o_descriptor_wr  <= 1'b0 ;
		
        ov_pkt_bufid         <= 9'h0;
        o_pkt_bufid_wr       <= 1'h0;
        ov_pkt_bufid_cnt     <= 6'h0;
    end                              
    else begin
	    if(i_md_wr)begin
            //ov_pkt_bufid_cnt     <= iv_md[166] + iv_md[167] + iv_md[168] + iv_md[169] + iv_md[170] + iv_md[171] + iv_md[172] + iv_md[173] + iv_md[174] + iv_md[175] + iv_md[176] + iv_md[177] + iv_md[178] + iv_md[179] + iv_md[180] + iv_md[181] + iv_md[182] + iv_md[183] + iv_md[184] + iv_md[185] + iv_md[186] + iv_md[187] + iv_md[188] + iv_md[189] + iv_md[190] + iv_md[191] + iv_md[192] + iv_md[193] + iv_md[194] + iv_md[195] + iv_md[196] + iv_md[197] + iv_md[198];
            //ov_pkt_bufid_cnt     <= iv_md[166] + iv_md[167] + iv_md[168] + iv_md[169] + iv_md[170] + iv_md[171] + iv_md[172] + iv_md[173] + iv_md[174] + iv_md[175] + iv_md[176] + iv_md[177] + iv_md[178] + iv_md[179] + iv_md[180] + iv_md[181] + iv_md[182] + iv_md[183] + iv_md[184] + iv_md[185]+ iv_md[198];
          //  ov_pkt_bufid_cnt     <= iv_md[166] + iv_md[167] + iv_md[182] + iv_md[183] + iv_md[198];
			o_pkt_bufid_wr       <= 1'h1;
            ov_pkt_bufid         <= iv_md[148:140];
            ov_pkt_bufid_cnt     <= iv_md[166] + iv_md[167] + iv_md[168] + iv_md[169] + iv_md[198];
            
            ov_descriptor[2:0]      <= iv_md[114:112]; //priority
            ov_descriptor[16:3]     <= iv_md[128:115]; //FlowID
            ov_descriptor[27:17]    <= iv_md[139:129]; //Length
            ov_descriptor[36:28]    <= iv_md[148:140]; //BufID
            ov_descriptor[42:37]    <= iv_md[154:149]; //Inport
            ov_descriptor[43]       <= iv_md[155]; //BE_Match
            ov_descriptor[53:44]    <= iv_md[165:156]; //plan Slot
            ov_descriptor[86:54]    <= iv_md[198:166]; //OutPortBM
				if(|iv_md[198:166] == 1'b0)begin
                ov_descriptor[87]       <= 1'b1;   //Discard
			   end
				else begin
				    ov_descriptor[87]       <= iv_md[199];   //Discard
				end
            o_descriptor_wr         <= 1'b1 ;
        end
        else begin
            ov_descriptor    <= 88'b0;
            o_descriptor_wr  <= 1'b0 ;
            
            ov_pkt_bufid         <= 9'h0;
            o_pkt_bufid_wr       <= 1'h0;
            ov_pkt_bufid_cnt     <= 6'h0;                
        end
    end
end
endmodule
    